One approach for electrically connecting an IC die to the package is the flip-chip mounting approach which allows batch fabrication of connections between the IC die and the package. According to the flip-chip approach, solder balls are first formed on top of the bonding pads on the IC die. Then the IC die is placed face down on a package so that the solder balls on the IC die are aligned with corresponding pads provided on the package. The pads are electrically connected to pins or other electrical connections on the bottom of the package. The IC die is then heated, which causes the solder balls to flow, bonding the IC die to the package and forming the required electrical connections between the IC die and the package.
Consider the flip-chip IC assembly 100 illustrated in FIG. 1. IC assembly 100 includes an IC die 102 and a package 104, which together mate with a socket 106. IC die 102 is cut from a processed wafer and contains a number of circuit devices 108. Electrically conductive solder balls 110, also known as flip-chip bumps, are provided on the bottom of IC die 102 and are electrically connected to circuit devices 108 via electrical connections 112.
In general, package 104 provides electrical connections between circuit devices 108 contained in IC die 102 and socket 106. A number of electrically conductive pads 114 are provided on top of package 104. Pads 114 are physically arranged on package 104 to correspond with the physical arrangement of solder balls 110 to provide electrical connections between IC die 102 and package 104. Pads 114 are electrically connected to an array of electrically conductive pins 116 provided on the bottom of package 104 via electrical connections 118. Pins 116 are arranged on the bottom of package 104 to mate with a series of corresponding holes 120 in socket 106 to provide electrical connections between package 104 and socket 106. When the number of pins 116 becomes large, package 104 can be many times larger than IC die 102. Package 104 can be made from a variety of materials such as plastic, ceramic or other composite material.
The flip-chip approach allows hundreds of bonds between an IC die and package to be formed simultaneously which reduces the time required to fabricate an IC assembly and provides more robust electrical connections between the IC die and package. In addition, the solder balls may be placed anywhere on the surface of the IC die, rather than only around the periphery. This allows a smaller package to be used as well as shorter wire lengths between the solder balls on the IC die and the lead wires on the package.
The flip-chip approach has some challenges. Specifically, the physical location of the solder balls on the IC die must closely match the physical location of the pads on the package to ensure that the desired electrical connections will be made when the IC die is joined with the package. Some deviation between the physical location of a solder ball on an IC die and the physical location of a corresponding pad on the package can result in a misconnection, rendering the package useless. In addition, electrical signals associated with the solder balls on the IC die must match electrical signals associated with the corresponding pads on the package. That is, each solder ball on the IC die must receive the correct electrical signal from its corresponding pad on the package, which in turn is provided to the corresponding pin on the package form the socket.
Current approaches for verifying the design of an IC package involve a manual comparison of solder ball location and signal data to pad location and signal data to verify the physical and logical interfaces between the IC die and the package. Such a manual comparison can be very time consuming, particularly when the number of electrical connections is large, and does not guarantee that the IC die will correctly mate with the package. Often the manual check is supplemented by a physical inspection and experimental testing of the IC after assembly. However, a visual inspection of a flip-chip IC after assembly can be difficult because of the inaccesability to the inner connections between an IC die and the package.
In view of the necessity to verify the design of an IC package prior to IC assembly and the limitations in existing approaches for accomplishing this task, there is a need for an automated approach for verifying the design of an IC package.